Along with an increase in the integration degree of semiconductor devices, electrodes and interconnects constituting them have become finer. Since interconnect width is also refined correspondingly, resistance of electrodes and interconnects is increased to make a considerable delay in signals and it has become difficult to design high speed and high performance integrated circuits. Particularly, since polycrystalline silicon used generally for gate electrodes and interconnects of existent MOS (Metal-Oxide-Semiconductor) type semiconductor devices has a relatively high resistance as about 1 mΩ·cm, decreasing the resistance of the electrodes and the interconnects is an important key to attain a high speed and highly integrated circuit. For the lowering of the resistance in the silicon layer, it has been generally studied a technique of vapor depositing titanium and cobalt and reacting the metals only to the electrode interconnect portions in a semiconductor device where silicon is exposed, thereby forming a metal silicide of low resistance, that is, self-aligned silicidation technique has been put to practical use. However, in the interconnects (electrodes) using the silicides, particularly, titanium silicide, when the interconnect width (electrode width) is refined to less than about 0.5 μm, it results in a problem that the resistance of the silicide layer itself is not lowered as in a case where the interconnect width (electrode width) is large.
Therefore, it has now been under study for gate electrodes and interconnects capable of ensuring stable MOS (transistor) electric characteristics, comparable with those of polycrystalline silicon gate electrodes and interconnects used so far, having lower resistance than silicides and with no increase in the resistivity even when the interconnect width (electrode width) is refined to 0.5 μm or less.
In recent years, as gate electrodes and interconnects suitable to the purpose described above, it has generally been studied for structures in which a polycrystalline silicon film and a tungsten film are stacked to each other and a barrier layer comprising a nitride of tungsten or titanium is disposed between the metal films and the silicon film. In the structures, since the metal film such as of tungsten scarcely reacts with the underlying silicon layer, gate electrode/interconnect having a low sheet resistance about equal with that of the single metal layer even after the heat treatment can be attained. Due to the effect of the low resistance interconnects (electrodes), high speed operation can be expected for highly integrated circuit semiconductor devices.
Since the silicide reaction does not occur in the stacked structure of the refractory metal layer/barrier layer/silicon layer described above, it has a merit capable of forming electrodes and interconnects by utilizing the low resistivity of the upper refractory metal layer as it is. The laminated film is fabricated into a gate electrode/interconnect pattern, for example, by a dry etching method. In this fabrication step, the gate oxide film present on the surface of the silicon substrate in the vicinity of the electrodes/interconnects are damaged and when a semiconductor device is manufactured in the state as it is, it results in a problem such as deterioration for the break down voltage of the gate insulator film or the long time reliability of the MOS transistor. The situation is identical also in existent gate electrodes/interconnects comprising a single polycrystalline silicon layer. Accordingly, it has generally been adopted to use a method of fabricating into an electrode/interconnect configuration, then removing peripheral silicon oxide film once and forming a clean silicon oxide film again, or repairing defective portions by a heat treatment in an oxidizing atmosphere without removal. The treatment described above is conducted at a high temperature of about 800° C. or higher. However, since the gate electrode of the stacked structure described above has a metal layer such as of tungsten which is readily oxidized or volatilized when exposed to an oxidizing atmosphere, re-oxidation of silicon described above is difficult. Then with a thermodynamical point of view, a heat treatment technique of conducting a heat treatment in an atmosphere where a controlled small amount of water is added to a hydrogen gas thereby capable of selectively oxidizing only the silicon without oxidizing the metals (rather metal oxides are reduced if present) (selective oxidation technology) has been provided and applied for higher reliability of the semiconductor device (refer to Patent Document 1, U.S. Pat. No. 6,197,702).
Further, Patent Document 2, JP-A No. 223439/2000, discloses a technique of nitriding the side wall of a gate electrode before a chemical solution cleaning step applied for removing an organic material (photoresist) adhered on the wafer surface to form a side wall protective film of tungsten nitride, thereby preventing corrosion of the tungsten film with a solution corroding the tungsten film (mixture of sulfuric acid and aqueous hydrogen) (refer to Patent Document 2).
Further, Patent Document 3, JP-A No. 243753/2000, discloses a technique of applying annealing in an NH3 gas atmosphere at 800 to 1150° C. after the patterning step for the gate line, thereby nitriding an exposed portion on the side of the patterned gate line to form a tungsten nitride layer, and preventing abnormal oxidation for the tungsten film (refer to Patent Document 3).
Further, Patent Document 4, JP-A No. 93743/2002, describes a technique of nitriding the surface of a tungsten film for a gate electrode after patterning the gate electrode thereby preventing occurrence of whiskers upon forming the side wall with a silicon nitride to the side wall of the gate electrode (refer to Patent Document 4).
The reliability relevant to the gate insulator film for the MOS transistor or the like has been improved outstandingly by the selective silicon oxidation technology described above (heat treatment in the atmosphere where a controlled small amount of water is added to hydrogen gas) However, according to the study made by the present inventors, an additional problem has been found relating to the heat treatment. That is, when the heat treatment (selective oxidation) is conducted at a temperature of 700° C. or higher, metal such as tungsten is oxidized at the boundary of the stacked structure: Particularly; when the gate electrodes/interconnects are refined to about 0.2 μm or less, oxidizing species (oxygen or water) diffuse from the side wall of the gate electrode to the boundary between the polycrystalline silicon and the barrier layer, or to the boundary between the barrier layer and the metal layer thereover, so that the contact resistance between the polycrystalline silicon layer and the barrier layer or the metal layer thereover increases in the order of the digit, which results in a problem that high speed operation of the semiconductor device becomes difficult due to the high contact resistance. Further, the oxides are formed on the metal layer surface exposed to the side wall in the fabrication step for gate electrode/interconnects and in the subsequent cleaning step. When selective oxidation is conducted in this state, oxides on the side wall volatilize during the heat treatment process which adhere on the silicon substrate exposed near the electrodes/interconnects or damaged silicon oxides, and metal contaminates intrude into the substrate to bring about a problem of degradation in the charge retention characteristics of the semiconductor device such as a memory, increase of the leak current at the junction layer such as source—drain and, further, deterioration of the dielectric breakdown of the gate insulator film.
Further, the technique for the nitrildation of the gate electrode is adopted for preventing corrosion by chemical solution, preventing abnormal oxidation of the tungsten film or preventing growth of whiskers during formation of the side wall and it does not solve the foregoing problems in view of the selective silicon oxidation technique.
Accordingly, it has been demanded to provide a semiconductor device capable of high speed operation and having high reliability by repairing damages or defects in the silicon oxide films in the vicinity of gate electrodes/interconnects caused in the step such as dry etching avoiding increase in the interlayer contact resistance in the gate electrode of the stacked structure and decreasing contamination to the silicon substrate caused by the metal layer side wall of electrodes/interconnects.